Skip to content
IJAIST

IJAIST

  • Home
  • EDITORIAL BOARD
  • REVIEWER BOARD
  • PUBLICATIONS
    • 2012 ISSUES
    • 2013 ISSUES
    • 2014 ISSUES
    • 2015 ISSUES
    • 2016 ISSUES
    • 2017 ISSUES
    • 2018 ISSUES
    • 2019 ISSUES
    • 2020 ISSUES
    • 2021 ISSUES
    • 2023 ISSUES
  • For Authors
    • Format & Style
    • General instructions
    • References
    • Contributions
  • CALL FOR PAPERS
  • INDEXING
  • ONLINE SUBMISSION
  • CONTACT
2013 APRIL ISSUE 

Hybrid Low Power Design for Adders Using SP-D3L

August 11, 2018 Editor IJAIAT 0 Comments
HybridLowPowerDesignforAddersUsingSPD3L

DOWNLOAD THIS PAPER HERE

File Description File size Downloads
pdf HybridLowPowerDesignforAddersUsingSPD3L 320 KB 717
  • ← A Modified-Time-Sharing Switching Technique for Multiple-Input DC–DC Converters by using Fuzzy Logic Controller
  • An energy efficient flip flop for three- phase dual – rail pre- charge logic family Using transmission gates →

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Copyright © 2025 IJAIST. All rights reserved.
Theme: ColorMag by ThemeGrill. Powered by WordPress.